Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films

This technology is used in fabrication of high voltage and high power electronics.

In SiC bipolar devices, basal plane dislocations (BPDs) in the active region generate Shockley-type stacking faults (SFs) and increase the forward voltage drift. For a sufficient yield of bipolar devices, the density of these performance-limiting defects in the epitaxial layer must be limited. One current method to reduce BPDs employs a defect selective etch of the SiC substrate by conventional molten KOH prior to epitaxial growth. However, this method severely degrades the epilayer. The epilayer must then be polished before device fabrication. Recently, a "growth-etch-regrowth" method was developed to achieve a BPD-free epilayer with almost no surface degradation. However, this method doubled the number of steps in epigrowth. Therefore, there was a need for a practically improved method of reducing BPDs in a SiC epitaxial film without substantially, adversely affecting the surface morphology of the SiC substrate.

This process has been developed and optimized for non-destructive pre-treatment of the SiC substrate. The technique allows the pre-treatment of the SiC substrate for reduction or elimination of basal plane dislocation and in-grown stacking faults in SiC epitaxial films. The method is a simple (three-minute treatment), non-destructive, and highly efficient process for the reduction of BPDs and SFs in the epitaxial film. It preserves a high BPD conversion rate. It shows high potential to be applied as one of the routine treatment steps prior to SiC epitaxial growth, which is one of the most important steps to fabricate various "state of the art" electronic and optical devices.